Semiconductor
Introduction to design methodology of digital system: FPGA design flow, logic synthesis and verification. Introduction to Verilog HDL: basic syntax and constructs, Verilog operators, structural modeling, dataflow modeling, behavioral modeling, delay. Programmable logic devices: SPLD, CPLD, FPGA. Digital system design (case study): Booth multiplier, UART design, FIR filter, LMS adaptive filter.
Created by Prof. Arighna Deb
Starts on
NIL
20 April 2023
10 June 2023
UG
ONLINE/OFFLINE
Introduction to design methodology of digital system: FPGA design flow, logic synthesis and verification.
Introduction to Verilog HDL: basic syntax and constructs, Verilog operators, structural modeling, dataflow modeling, behavioral modeling, delay.
Programmable logic devices: SPLD, CPLD, FPGA.
Digital system design (case study): Booth multiplier, UART design, FIR filter, LMS adaptive filter.
Understand the detailed steps involved in the digital system design.
Gain knowledge of Verilog HDL, a programming language for digital system design.
Understand how to use Vivado software for synthesizing and simulating Verilog codes.
Implement digital systems in FPGA devices.
Skills you will gain:
Steps to design digital system, FPGA architecture, Verilog HDL, Vivado software.
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