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Semiconductor

DIGITAL SYSTEM AND ITS FPGA IMPLEMENTATION

Introduction to design methodology of digital system: FPGA design flow, logic synthesis and verification. Introduction to Verilog HDL: basic syntax and constructs, Verilog operators, structural modeling, dataflow modeling, behavioral modeling, delay. Programmable logic devices: SPLD, CPLD, FPGA. Digital system design (case study): Booth multiplier, UART design, FIR filter, LMS adaptive filter.

Created by Prof. Arighna Deb

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Prerequisite

NIL

Start Date

20 April 2023

End Date

10 June 2023

Level

UG

Enrollment options

ONLINE/OFFLINE

Course Description

Introduction to design methodology of digital system: FPGA design flow, logic synthesis and verification.

Introduction to Verilog HDL: basic syntax and constructs, Verilog operators, structural modeling, dataflow modeling, behavioral modeling, delay.

Programmable logic devices: SPLD, CPLD, FPGA.

Digital system design (case study): Booth multiplier, UART design, FIR filter, LMS adaptive filter.


Learning Outcomes

 Learners will be able to

Understand the detailed steps involved in the digital system design.

Gain knowledge of Verilog HDL, a programming language for digital system design.

Understand how to use Vivado software for synthesizing and simulating Verilog codes.

Implement digital systems in FPGA devices.

Skills you will gain:

Steps to design digital system, FPGA architecture, Verilog HDL, Vivado software.

Course Instructor

Prof. Arighna Deb

Prof. Arighna Deb

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